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this is information on a product in full production. july 2015 docid15534 rev 7 1/32 L6599AT improved high voltage resonant controller datasheet - production data features ? 50% duty cycle, variable frequency control of resonant half bridge ? high accuracy oscillator ? up to 500 khz operating frequency ? two-level ocp: frequency-shift and latched shutdown ? interface with pfc controller ? latched disable input ? burst mode operation at light load ? input for power-on/off sequencing or brownout protection ? non-linear soft-start for monotonic output voltage rise ? 600 v - rail compatible high-side gate driver with integrated bootstra p diode and high dv/dt immunity ? -300/700 ma high-side and low-side gate drivers with uvlo pull-down ? guaranteed for extreme temperature ranges applications ? lcd and pdp tv ? desktop pc, entry-level server ? telecom smps ? high efficiency industrial smps ? ac-dc adapter, open frame smps 61 table 1. device summary order code package packaging L6599ATd so16n tube L6599ATdtr tape and reel www.st.com
contents L6599AT 2/32 docid15534 rev 7 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 current sense, ocp and olp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5 latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6 line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.7 bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 so16n package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
docid15534 rev 7 3/32 L6599AT description 32 1 description the L6599AT is an improved revision of the prev ious l6599a. it is a double-ended controller specific to series-resonant half bridge topology . it provides 50% complementary duty cycle: the high-side switch and the low-side switch are driven on/off 180 out-of-phase for exactly the same time. output voltage regulation is obtained by modulating the operating frequency. a fixed deadtime inserted between t he turn-off of one switch and the turn-on of the other guarantees soft-switching and enables high-frequency operation. to drive the high-side switch with the bootstra p approach, the ic incorporates a high voltage floating structure able to withstand more than 600 v with a synchronous-driven high voltage dmos that replaces the external fast-recovery bootstrap diode. the ic enables the designer to set the operating frequency range of the converter by means of an externally programmable oscillator. at startup, to prevent uncontrolled inrush current, the switching frequency starts from a programmable maximum value and progressively decays until it reaches the steady-state value determined by the control loop. this frequ ency shift is non-linear to minimize output voltage overshoots; its duration is programmable as well. at light load the ic may enter a controlled bu rst mode operation that keeps the converter input consumption to a minimum. ic functions include a not-latched active-low di sable input with current hysteresis useful for power sequencing or for brownout protection, a current sense input for ocp with frequency shift and delayed shutdown with automatic restar t. a higher level ocp latches off the ic if the first-level protection is not sufficient to control the prim ary current. their combination offers complete protection against overload and short-circuits. an additional latched disable input (dis) allows easy implem entation of otp and/or ovp. an interface with the pfc controller is provided that enables the pre-regulator to be switched off during fault conditions, such as ocp shutdown and dis high, or during burst mode operation.
block diagram L6599AT 4/32 docid15534 rev 7 2 block diagram figure 1. block diagram 9ff 9 %227 +9 ',6$%/( ',6 287 & %227 /&7$1. &,5&8,7 89 '(7(&7,21 9ff +9* 6<1&+521286 %227675$3',2'( +9* '5,9(5 ',6 /(9(/ 6+,)7(5 9 64 5 89/2 89/2 ',6 9 9 67$1'%< 67%< '5,9,1* *1' ,iplq ,6(1 9 /9* /9* '5,9(5 &vv '($' 7,0( 5)plq 46 5 89/2 ,6(1b',6 '5,9,1* /2*,& 9 67$1'%< ',6 ,6(1b',6 9 3)&b6723 &) &21752/ /2*,& /,1(b2. 9 ?$ 9 2&3 9&2 /,1( '(/$< $0y
docid15534 rev 7 5/32 L6599AT pin connection 32 3 pin connection figure 2. pin connection (top view) $0y *1' &vv ' (/$< 67%< ,6(1 /,1( /9* 9%227 +9* 1& 9ff 3)&b672 3 287 ',6 &) 5)plq table 2. pin description pin no. type function 1css soft-start. this pin connects an external capacitor to gnd and a resistor to rfmin (pin 4) that set both the maximum oscillator frequency and the time constant for the frequency shift that occurs as the chip starts up (soft-start) . an internal switch di scharges this capacitor every time the chip turns off (vcc < uvlo, line < 1.24 v or > 6 v, dis > 1.85 v, isen > 1.5 v, delay > 2 v) to make sure it is soft-started next, and when the voltage on the current sense pin (isen) exceeds 0.8 v, as long as it stays above 0.75 v. 2delay delayed shutdown upon overcurrent. a capacitor and a resistor are connected from this pin to gnd to set the maximum duration of an overcurrent condition before the ic stops switching and the delay after which the ic rest arts switching. every time the voltage on the isen pin exceeds 0.8 v, the capacitor is char ged by an internal 150 a current generator and is slowly discharged by the external resist or. if the voltage on the pin reaches 2 v, the soft-start capacitor is completely discharged so that the switching frequency is pushed to its maximum value and the 150 a is kept always on. as the voltage on the pin exceeds 3.5 v the ic stops switching and the internal generator is turned off, so that the voltage on the pin decays because of the external resistor. the ic is soft-restarted as the voltage drops below 0.3 v. in this way, under short-circuit conditio ns, the converter works intermittently with very low input average power. 3cf timing capacitor. a capacitor connected from this pin to gnd is charged and discharged by internal current generators programmed by the external network connected to pin 4 (rfmin) and determines the switching frequency of the converter. 4rfmin minimum oscillator frequency setting. this pi n provides a precise 2 v reference and a resistor connected from this pin to gnd define s a current that is us ed to set the minimum oscillator frequency. to close the feedback loop that regulates the converter output voltage by modulating the oscillator frequency, the phot otransistor of an optocoupler is connected to this pin through a resistor. the value of this resistor sets the maximum operating frequency. an r-c series connected from this pin to g nd sets frequency shift at startup to prevent excessive energy inrush (soft-start).
pin connection L6599AT 6/32 docid15534 rev 7 5stby burst mode operation threshold. the pin sens es some voltage related to the feedback control, which is compared to an internal refere nce (1.24 v). if the voltage on the pin is lower than the reference, the ic enters an idle state and its quiescent current is reduced. the chip restarts switching as the voltage exceeds the re ference by 50 mv. soft-start is not invoked. this function realizes burst mode operation wh en the load falls below a level that can be programmed by properly choosing the resistor connecting the optocoupler to pin rfmin (see block diagram). tie the pin to rfmin if burst mode is not used. 6isen current sense input. the pin senses the pr imary current though a sense resistor or a capacitive divider for lossless sensing. this in put is not intended for a cycle-by-cycle control; therefore the voltage signal must be filtered to get average current information. as the voltage exceeds a 0.8 v threshold (with 50 mv hysteresis), the soft-start capacitor connected to pin 1 is internally discharged: the frequency increases, so limiting the power throughput. under output short-circuit, this normally results in a nearly constant peak primary current. this condition is allowed for a maximum time set at pin 2. if the current keeps on building up despite this frequency incr ease, a second comparator referenced at 1.5 v latches the device off and brings its cons umption almost to a ?before startup? level. the information is latched and it is necessary to recycle the supply voltage of the ic to enable it to restart: the latch is removed as the voltage on the vcc pin goes below the uvlo threshold. tie the pin to gnd if the function is not used. 7line line sensing input. the pin is to be connected to the high voltage input bus with a resistor divider to perform either ac or dc (in system s with pfc) br ownout protection. a voltage below 1.24 v shuts down (not latched) the ic, lowers its consumption and discharges the soft-start capacitor. ic operation is re-enabled (soft-started) as the voltage exceeds 1.24 v. the comparator is provided with current hysteresis: an internal 13 a current generator is on as long as the voltage applied at the pin is below 1.24 v and is off if this value is exceeded. bypass the pin with a capacitor to gnd to reduce noise pick-up. the voltage on the pin is top-limited by an internal zener diode. activating the zener diode causes the ic to shut down (not latched). bias the pin betw een 1.24 and 6 v if the function is not used. 8dis latched device shutdown. internally, the pin connects a comparator that, when the voltage on the pin exceeds 1.85 v, shuts the ic down a nd brings its consumpti on almost to a ?before startup? level. the information is latched and it is necessary to recycle the supply voltage of the ic to enable it to restart: the latch is removed as the voltage on the vcc pin goes below the uvlo threshold. tie the pin to gnd if the function is not used. 9pfc_stop open-drain on/off control of pfc controller . this pin, normally open, is intended for stopping the pfc controller, for protection purp oses or during burst mode operation. it goes low when the ic is shut down by dis>1.85 v, isen > 1.5 v, line > 6 v and stby < 1.24 v. the pin is pulled low also when the voltage on the delay exceeds 2 v and goes back open as the voltage falls below 0.3 v. during uvlo , it is open. leave the pin unconnected if not used. 10 gnd chip ground. current return for both the low- side gate-drive current and the bias current of the ic. all of the ground connections of the bi as components should be tied to a track going to this pin and kept separate from any pulsed current return. 11 lvg low-side gate-drive output. the driver is cap able of 0.3 a min. source and 0.7 a min. sink peak current to drive the lower mosfet of the ha lf bridge leg. the pin is actively pulled to gnd during uvlo. 12 vcc supply voltage of both the signal part of the ic and the low-side gate driver. sometimes a small bypass capacitor (0.1 f typ.) to gnd may be useful to get a clean bias voltage for the signal part of the ic. table 2. pin description (continued) pin no. type function
docid15534 rev 7 7/32 L6599AT pin connection 32 13 n.c. high voltage spacer. the pin is not internally connected to isolate the high voltage pin and ease compliance with safety regulations (creepage distance) on the pcb. 14 out high-side gate-drive floating grou nd. current return for the high-side gate-drive current. layout carefully the connection of this pi n to avoid too large spikes below ground. 15 hvg high-side floating gate-drive output. the driver is capable of 0.3 a min. source and 0.7 a min. sink peak current to drive the upper mosfet of the half bridge leg. a resistor internally connected to pin 14 (out) ensures that the pin is not floating during uvlo. 16 vboot high-side gate-drive floating supply voltage. the bootstrap capacitor connected between this pin and pin 14 (out) is fed by an inter nal synchronous bootstrap diode driven in-phase with the low-side gate drive. this patented structure replaces the normally used external diode. table 2. pin description (continued) pin no. type function
electrical data L6599AT 8/32 docid15534 rev 7 4 electrical data 4.1 absolute maximum ratings note: esd immunity for pins 14, 15 and 16 is guaranteed up to 900 v. 4.2 thermal data table 3. absolute maximum rating symbol pin parameter value unit v boot 16 floating supply voltage -1 to 618 v hvg 15 hvg voltage v out -0.3 to v boot +0.3 v v out 14 floating ground voltage -3 up to a value included in the range v boot -18 and v boot v dv out /dt 14 floating ground max. slew rate 50 v/ns vcc 12 ic supply voltage (icc = 25 ma) self-limited v lvg 11 lvg voltage -0.3 to v cc +0.3 v v pfc_stop 9 maximum voltage (pin open) -0.3 to vcc v i pfc_stop 9 maximum sink current (pin low) self-limited a v linemax 7 maximum pin voltage (ipin ? 1 ma) self-limited v i rfmin 4 maximum source current 2 ma --- 1 to 6, 8 analog inputs and outputs -0.3 to 5 v ptot power dissipation at t a = 70 c (dip16) 1 w power dissipation at t a = 50 c (so16) 0.83 tj junction temperature operating range -40 to 150 c tstg storage temperature -55 to 150 c table 4. thermal data symbol parameter value unit r th(ja) max. thermal resistance junction to ambient (so16) 120 c/w
docid15534 rev 7 9/32 L6599AT electrical characteristics 32 5 electrical characteristics t j = - 40 to 125 c, v cc = 15 v, vboot = 15 v, c hvg = c lvg = 1 nf; c f = 470 pf; r rfmin = 12 k ? ; unless otherwise specified. table 5. electrical characteristics symbol parameter test condition min. typ. max. unit ic supply voltage vcc operating range after device turn-on 8.85 16 v vcc on turn-on threshold voltage rising 10 10.7 11.4 v vcc off turn-off threshold voltage falling 7.45 8.15 8.85 v hys hysteresis 2.55 v v z vcc clamp voltage iclamp = 15 ma 16 17 v supply current i start-up startup current before device turn-on vcc = vcc on - 0.2 v 200 250 a i q quiescent current device on, v stby = 1 v 1.5 2 ma i op operating current device on, v stby = v rfmin 3.5 5 ma i q residual consumption v dis > 1.85 v or v delay > 3.5 v or v line < 1.24 v or v line = v clamp 300 400 a high-side floating gate-drive supply i lkboot v boot pin leakage current v boot = 580 v 5 a i lkout out pin leakage current v out = 562 v 5 a r ds(on) synchronous bootstrap diode on-resistance v lvg = high 150 ? overcurrent comparator i isen input bias current v isen = 0 to v isendis -1 a t leb leading edge blanking after v hvg and v lvg low-to-high transition 250 ns v isenx frequency shift threshold voltage rising (1) 0.76 0.8 0.84 v hysteresis voltage falling 50 mv v isendis latch-off threshold voltage rising (1) 1.44 1.5 1.56 v td (h-l) delay to output 300 400 ns line sensing vth threshold voltage voltage rising or falling (1) 1.2 1.24 1.28 v i hys current hysteresis v line = 1.1 v 10 13 16 a v clamp clamp level i line = 1 ma 6 8 v
electrical characteristics L6599AT 10/32 docid15534 rev 7 dis function i dis input bias current v dis = 0 to vth -1 a vth disable threshold voltage rising (1) 1.78 1.85 1.92 v oscillator d output duty cycle both hvg and lvg 48 50 52 % f osc oscillation frequency 58.2 60 61.8 khz r rfmin = 2.7 k ? 240 250 260 t d deadtime between hvg and lvg 0.2 0.3 0.4 s v cfp peak value 3.9 v v cfv valley value 0.9 v v ref voltage reference at pin 4 (1) 1.93 2 2.07 v i ref = -2 ma (1) 1.8 2 2.2 k m current mirroring ratio 1 a/a pfc_stop function i leak high level leakage current v pfc_stop = vcc, v dis = 0 v 1 a r pfc_stop on-state resistance i pfc_stop = 1 ma, v dis = 1.5 v 130 200 ? v l low saturation level i pfc_stop = 1 ma, v dis = 1.5 v 0.2 v soft-start function i leak open-state current v(css) = 2 v 0.5 a r discharge resistance v isen > v isenx 120 ? standby function i dis input bias current v dis = 0 to vth -1 a vth disable threshold voltage falling (1) 1.2 1.24 1.28 v hys hysteresis voltage rising 50 mv delayed shutdown function i leak open-state current v(delay) = 0 0.5 a i charge charge current v delay = 1 v, v isen = 0.85 v 100 150 200 a vth 1 threshold for forced operation at max. frequency voltage rising (1) 1.98 2.05 2.12 v vth 2 shutdown threshold voltage rising (1) 3.35 3.5 3.65 v vth 3 restart threshold voltage falling (1) 0.3 0.33 0.36 v table 5. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
docid15534 rev 7 11/32 L6599AT electrical characteristics 32 low-side gate driver (voltages referred to gnd) v lvgl output low voltage i sink = 200 ma 1.8 v v lvgh output high voltage i source = 5 ma 12.8 13.3 v i sourcepk peak source current -0.3 a i sinkpk peak sink current 0.7 a t f fall time 30 ns t r rise time 60 ns uvlo saturation vcc = 0 to vcc on , i sink = 2 ma 1.1 v high-side gate driver (v oltages referred to out) v lvgl output low voltage i sink = 200 ma 1.8 v v lvgh output high voltage i source = 5 ma 12.8 13.3 v i sourcepk peak source current -0.3 a i sinkpk peak sink current 0.7 a t f fall time 30 ns t r rise time 60 ns hvg-out pull-down 25 k ? 1. values tracking each other. table 5. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
application information L6599AT 12/32 docid15534 rev 7 6 application information the L6599AT is an advanced double-ended controller specific fo r resonant half bridge topology (see figure 4 ). in these converters the switches (mosfets) of the half bridge leg are alternately switched on and off (180 out-of- phase) for exactly the same time. this is commonly referred to as operation at ?50% duty cycle?, although the real duty cycle, that is the ratio of the on-time of either switch to th e switching period, is ac tually less than 50%. the reason is that there is an internally fixed deadtime t d inserted between the turn-off of either mosfet and the turn-on of the other one, where both mosfets are off. this deadtime is essential in order for the converte r to work correctly: it ensures soft-switching and enables high-frequency operation with high efficiency and low emi emissions. to perform converter output voltage regulation the device is able to operate in different modes ( figure 3 ), depending on the load conditions: 1. variable frequency at he avy and medium/light load. a relaxation oscillator (see section 6.1: oscillator for more details) generates a symmetrical triangular waveform, which the mosfet switching is locked to. the frequency of th is waveform is related to a current that is modulated by the feedback circ uitry. as a result, the tank circuit driven by the half bridge is stimulated at a frequ ency dictated by the feedback loop to keep the output voltage regulated, therefore expl oiting its frequency-dependent transfer characteristics. 2. burst mode control with no or very light load. when the load falls below a value, the converter enters a controlled intermittent op eration, where a series of a few switching cycles at a nearly fixed frequency are spac ed out by long idle periods where both mosfets are in off-state. a further load decrease is translated into longer idle periods and then in a reduction of the average switching frequency. when the converter is completely unloaded, the average switching frequency can go down even to few hundred hertz, therefore minimizing magnetizing current losses as well as all frequency-related losses and making it easier to comply with energy saving recommendations. figure 3. multi-mode operation of the L6599AT $0y i vz 3 lq 9duldeohiuhtxhqf\prgh 3lqp d [ %xuvwprgh 9 lq
docid15534 rev 7 13/32 L6599AT application information 32 figure 4. typical system block diagram 6.1 oscillator the oscillator is programmed ex ternally by means of a capaci tor (cf), connected from the pin 3 (cf) to ground, that is alternately char ged and discharged by the current defined with the network connected to pin 4 (rf min ). the pin provides an accurate 2 v reference with about 2 ma source capability a nd the higher the current sourced by the pin is, the higher the oscillator frequency is. the block diagram of figure 5 shows a simplified internal circuit that explains the operation. the network that loads the r fmin pin is generally made up of three branches: 1. a resistor rf min connected between the pin and ground that determines the minimum operating frequency. 2. a resistor rf max connected between the pin and the collector of the (emitter-grounded) phototransistor that tr ansfers the feedback signal from the secondary side back to the primary side; while in operation, the phototr ansistor modulates the current through this branch - therefore modulating the oscillat or frequency - to perform output voltage regulation; the value of rf max determines the maximum frequency the half bridge is operated at when the phototransistor is fully saturated. 3. an r-c series circuit (css+rss) connected between the pin and ground that enables a frequency shift to be set up at startup (see section 6.3: soft-start on page 18 ). note that the contribution of this branch is zero during steady-state operation. $0y ? 9 lqdf 9 rxwgf '$3 5hvrqdqw+%lvwxuqhgriilqfdvhri 3)&
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application information L6599AT 14/32 docid15534 rev 7 figure 5. oscillator internal block diagram the following approximate relati onships hold for the minimu m and the maximum oscillator frequency respectively: equation 1 after fixing cf in the hundred pf or in the nf (consistently with the maximum source capability of the rf min pin and trading this off against the total consumption of the device), the value of rf min and rf max is selected so that the oscillato r frequency is able to cover the entire range needed for regulation, from the minimum value f min (at minimum input voltage and maximum load) to the maximum value f max (at maximum input voltage and minimum load): equation 2 a different selection criterion is given for r fmax in case burst mode operation at no load is used (see section 6.2: operation at no load or very light load ). 9 5)plq &) 6 4 5 9 9 &) , 5 . 0 , 5 . 0 , 5 5)plq . 0 , 5 5vv 5 )pd[ &vv /$ 9 5)plq &) 6 4 5 9 9 &) , 5 . 0 , 5 . 0 , 5 5)plq . 0 , 5 5vv 5 )pd[ &vv 9 5)plq &) 6 4 5 9 9 &) , 5 . 0 , 5 . 0 , 5 5)plq . 0 , 5 5vv 5 )pd[ &vv /$7 9 5)plq &) 6 4 5 9 9 &) , 5 . 0 , 5 . 0 , 5 5)plq . 0 , 5 5vv 5 )pd[ &vv $0y ?? max min max min min rf // rf cf 3 1 f ; rf cf 3 1 f ? ? ? ? ? ? 1 f f rf rf ; f cf 3 1 rf min max min max min min ? ? ? ? ?
docid15534 rev 7 15/32 L6599AT application information 32 figure 6. oscillator waveforms and thei r relationship with gate-driving signals in figure 6 the timing relationship between the oscillator waveform and the gate-drive signal, as well as the swinging node of the half bridge leg (hb), is shown. note that the low- side gate drive is turned on while the oscillator triangle is ramping up and the high-side gate drive is turned on while the tria ngle is ramping down. in this way, at startup, or as the ic resumes switching during burst mode operation, the low-side mosfet is switched on first to charge the bootstrap capacitor. as a result, the bootstrap capacitor is always charged and ready to supply the high-side floating driver. 6.2 operation at no lo ad or very light load when the resonant half bridge is lightly loaded or not loaded at all, its switching frequency is at its maximum value. to keep the output voltage under control in these conditions and to avoid losing soft-switching, there must be some significant residual current flowing through the transformer?s magnetizing inductance. this current, however, produces some associated losses that prevent converter no load consumption from achieving very low values. to overcome this issue, the L6599AT enables the designer to make the converter operate intermittently (burst mode operation), with a se ries of a few switching cycles spaced out by long idle periods where both mosfets are in off-state, so that the average switching frequency can be substantially reduced. as a result, the average value of the residual magnetizing current and the associated losses are considerably cut down, therefore facilitating the converter to comply with energy saving recommendations. the L6599AT can be operated in burst mode by using pin 5 (stby): if the voltage applied to this pin falls below 1.24 v, the ic enters an id le state where both gate-drive outputs are low, the oscillator is stopped, the so ft-start capacitor css keeps its charge and only the 2 v reference at the rf min pin stays alive to minimize ic consumption and vcc capacitor discharge. the ic resumes normal operation as the voltage on the pin exceeds 1.24 v by 50 mv. to implement burst mode operation the voltage applied to the stby pin needs to be related to the feedback loop. figure 7 (a) shows the simplest implementation, suitable with a narrow input voltage range (e.g. when there is a pfc front-end). $0y &) + 9* w w / 9* w +% w 7 ' 7 '
application information L6599AT 16/32 docid15534 rev 7 figure 7. burst mode implementation: a) narrow input voltage range; b) wide input voltage range essentially, rf max defines the switching frequency f max above which the L6599AT enters burst mode operation. once f max is fixed, rf max is found from the relationship: equation 3 note that, unlike the f max considered in the previous section ( section 6.1: oscillator ), here f max is associated to some load pout b greater than the minimum one. pout b is such that the transformer peak currents are low enough not to cause audible noise. resonant converter switching frequency, however, depends also on the input voltage; therefore, in the case of quite a large input voltage range with the circuit of figure 7 a, the value of pout b would change considerab ly. in this case it is recommended to use the arrangement shown in figure 7 b, where the information on the converter input voltage is added to the voltage applied to the stby pin. due to the strongly non-linear relationship between switching frequency and input voltage, it is more practical to find empirically the right amount of correction r a / (r a + r b ) needed to minimize the change of pout b . make sure to choose the total value r a + r b much greater than r c to minimize the effect on the line pin voltage (see section 6.6: line sensing function on page 23 ). whichever circuit is in use, its operation can be described as follows. as the load falls below the value pout b the frequency tries to exceed the maximum programmed value f max and the voltage on the stby pin (v stby ) goes below 1.24 v. the ic then stops with both gate-drive outputs low, so that both mosfets of the half bridge leg are in off-state. the voltage v stby now increases as a result of the feedback reaction to the energy delivery stop and, as it exceeds 1.29 v, the ic restarts switching. after a while, v stby goes down again in response to the energy burst and stops the ic. in this way, the conv erter works in a burst mode fashion with a nearly constant switching frequency. a further load decrease then causes a frequency reduction, which can go down even to few hundred hertz. the timing diagram of figure 8 illustrates this kind of operation, showing the most significant signals. a small capacitor (typically in the hundred pf) from the stby pin to ground, placed as close to the ic as possible to reduce switching noise pick-up, helps obtain clean operation. to help the designer meet energy saving requirements even in power-factor-corrected systems, where a pfc pre-regulator precedes the dc-dc converter, the L6599AT allows that the pfc pre-regulator can be turned off during burst mode operation, therefore $0y d e '$3 67%< 5)plq 5 ) pl q 5 )pd[ '$3 67%< 5)plq 5 )plq 5 )pd[ /,1( 5 $ % 5 % 5 & 5 ' 5 $ 5 % !!5 & /$ /$ d e 67%< 5)plq 5 ) pl q 5 )pd[ '$3 67%< 5)plq 5 )plq 5 )pd[ /,1( 5 $ % 5 % 5 & 5 ' 5 $ 5 % !!5 & /$7 /$7 1 f f rf 8 3 rf min max min max ? ?
docid15534 rev 7 17/32 L6599AT application information 32 eliminating the no load consumpt ion of this stage (0.51 w). there is no compliance issue in that, because emc regulations on low-frequency harmonic emissions refer to nominal load, no limit is envisaged when the conver ter operates with light or no load. to do so, the L6599AT provides pin 9 (pfc_sto p): it is an open collector output, normally open, that is asserted low when the ic is idle during burst mode operation. this signal is externally used for switching off the pfc controller and the pre-regulator, as shown in figure 9 . when the L6599AT is in uvlo, the pin is kept open to let the pfc controller start first. figure 8. load-dependent operating modes: timing diagram figure 9. how the L6599AT can switch off a pfc controller at light load 67%< 9 w i rvf p9 k\vwhu /9* +9* w w 3)&b6723 5hvrqdqw0rgh %xuvwprgh 5hvrqdqw0rgh 3)& *$7('5,9( $0y $0y /$ 3)&b6723 /$ 9ff ,19 n ? n ? %& %& /$ 3)&b6723 /$6+ 3)&b2. $&b2. /$7 3)&b6723 /$ 9ff ,19 n ? n ? %& %& /$7 3)&b6723 /$6+ 3)&b2. $&b2.
application information L6599AT 18/32 docid15534 rev 7 6.3 soft-start generally speaking, the purpose of soft-start is to progressively increase converter power capability when it is started up, so as to avoid excessive inrush current. in resonant converters the deliverable power depends inversely on frequency, soft-start is then done by sweeping the operating frequency from an initial high value until the control loop takes over. with the L6599AT converter, soft-startup is simply realized with the addition of an r-c series circuit from pin 4 (rf min ) to ground (see figure 10 , left). initially, the capacitor c ss is totally discharged, so that the series resistor r ss is effectively in parallel to rf min and the resulting initial fr equency is determined by r ss and rf min only, since the optocoupler phototransistor is cut off (as long as the output voltage is not too far away from the regulated value): equation 4 the c ss capacitor is progressively charged until its voltage reaches the reference voltage (2 v) and, consequently, the current through r ss goes to zero. this conventionally is imposed 5 times by selecting the constants r ss c ss . before reaching 2 v on c ss , the output voltage should be already close to the regulated value and the feedback loop already taken over, so that it is the optocoupler phototransi stor to determine the operating frequency from that moment onwards. during this frequency sweep phase the operating frequency decays following the exponential charge of c ss , that is, initially it changes relati vely quickly but the rate of change gets slower and slower. this counteracts t he non-linear frequency dependence of the tank circuit that makes the converte r power capability change little as frequency is away from resonance and change very quickly as frequency approaches resonance frequency (see figure 10 , right). figure 10. soft-start circuit (left) and power vs. frequency curve in a resonant half bridge (right) as a result, the average input current smoothly increases, without the peaking that occurs with linear frequency sweep, and the output volt age reaches the regulated value with almost no overshoot. ?? ss min start r // rf cf 3 1 f ? ? ? $0y /$7 &vv 5)plq 5 )plq 5 66 & 66 5(621$1&( )5(48(1&< i _=i_ ,qlwldo iuhtxhqf\ 6whdg\vwdwh iuhtxhqf\
docid15534 rev 7 19/32 L6599AT application information 32 typically, r ss and c ss are selected based on the following relationships: equation 5 where f start is recommended to be at least 4 times f min . the proposed criterion for c ss is quite empirical and is a compromise between an effective soft-start action and an effective ocp (see next section). please re fer to the timing diagram of figure 10 to see some significant signals during the soft-start phase. 6.4 current sense, ocp and olp the resonant half bridge is essentially volt age-mode controlled; therefore a current sense input only serves as an overcurrent protection (ocp). unlike pwm-controlled converters, where energy fl ow is controlled by the duty cycle of the primary switch (or switches), in a resonant half bridge the duty cycle is fixed and energy flow is controlled by its switching frequency. this impacts on the way current limitation can be realized. while in pw m-controlled converters energy flow can be limited simply by terminating switch conduction beforehand w hen the sensed current exceeds a preset threshold (this is commonly known as cycle-by- cycle limitation), in a re sonant half bridge the switching frequency, that is, it s oscillator frequency must be increased and this cannot be done as quickly as turning off a switch: it takes at least the next oscillator cycle to see the frequency change. this implies that, to have an effective increase able to change the energy flow significantly, the rate of ch ange of the frequency must be slower than the frequency itself. this, in turn, implies that cycle-by-cycle limitat ion is not feasible and that, therefore, the information on the primary current fed to the current sensing input must be somehow averaged. of course, the averaging time must not be too long to prevent the primary current from reaching too high values. in figure 11 a couple of current sensing methods are illustrated and ar e described in the following. the circuit of figure 11 a is simpler but the dissipati on on the sense resistor rs might not be negligible, damaging efficiency; the circuit of figure 11 b is more complex but virtually lossless and recommended when the efficiency target is very high. ss 3 ss min start min ss r 10 3 c ; 1 f f rf r ? ? ? ? ?
application information L6599AT 20/32 docid15534 rev 7 figure 11. current sensing techniques: a) with se nse resistor, b) ?lossless?, with capacitive shunt the L6599AT is equipped with a current sensin g input (pin 6, isen) and a sophisticated overcurrent management system. the isen pin is internally connected to the input of a first comparator, referenced to 0.8 v, and to that of a second comparator referenced to 1.5 v. if the voltage externally applied to the pin by either circuit in figure 11 exceeds 0.8 v, the first comparator is tripped and this causes an internal switch to be turned on and discharge the soft-start capacitor c ss (see section 6.3: soft-start ). this quickly incr eases the oscillator frequency and thereby limits energy transfer. the discharge goes on until the voltage on the isen pin has dropped by 50 mv; this, with an averaging time in the range of 10/f min , ensures an effective frequency rise. under outpu t short-circuit, this operation results in a nearly constant peak primary current. it is normal that the voltage on the isen pin may overshoot above 0.8 v; however, if the voltage on the isen pin reaches 1.5 v, the second comparator is triggered, the L6599AT shuts down and latches off with both the gate drive outputs and the pfc_stop pin low, therefore turning off the entire unit. the supply voltage of the ic must be pulled below the uvlo threshold and then again above the startup level in order to restart. such an event may occur if the soft-start capacitor c ss is too large, so that its discharge is not fast enough or in the case of transformer magnetizing inductance saturation or a shorted secondary rectifier. in the circuit shown in figure 11 a, where a sense resistor rs in series to the source of the low-side mosfet is used, note the particular c onnection of the resonant capacitor. in this way the voltage across rs is related to the current flowing through the high-side mosfet and is positive most of the switching period , except for the time needed for the resonant current to reverse after the low-side mosfet has been switched off. assuming that the time constant of the rc filter is at leas t ten times the minimum switching frequency f min , the approximate value of rs can be found using the empirical equation: equation 6 where i crpkx is the maximum desired peak current flowing through the resonant capacitor and the primary winding of the transformer, which is related to the maximum load and the minimum input voltage. $0y d e '$3 ,6(1 t y i plq 5v &u 9vsn , &u '$3 ,6(1 &u 5 $ 5 % 1 & % & $ 1 t y i plq 9 &usn , &u /$ /$ d e '$3 ,6(1 t y i plq 5v &u 9vsn , &u '$3 ,6(1 &u 5 $ 5 % 1 & % & $ 1 t y i plq 9 &usn , &u /$7 /$7 crpkx crpkx crpkx pkx i 4 i 8 . 0 5 i vs rs ? ? ? ?
docid15534 rev 7 21/32 L6599AT application information 32 the circuit shown in figure 11 b can be operated in two diff erent ways. if the resistor r a in series to c a is small (not above some hundred ? , just to limit current spiking), the circuit operates like a capacitive current divider; c a is typically selected equa l to cr/100 or less and is a low-loss type, the sense resistor r b is selected as: equation 7 and c b is such that r b c b is in the range of 10 /f min . if the resistor r a in series to c a is not small (in this case it is typically selected in the ten k ? ), the circuit operates like a divider of the ri pple voltage across the resonant capacitor cr, which, in turn, is related to its current through the reactance of cr. again, c a is typically selected equal to cr/100 or less, not nece ssarily a low-loss type this time, while r b (provided it is << r a ) according to: equation 8 where the reactance of c a (x ca ) and cr (x cr ) should be calculated at the frequency where i crpk = i crpkx . again, c b is such that r b c b is in the range of 10 /f min . whichever circuit is used, the ca lculated values of rs or r b should be considered just a first cut value that needs to be adjusted after experimental verification. ocp is effective in limiting primary-to-secondary energy flow in case of an overload or an output short-circuit, but the output current through the secondary winding and rectifiers under these conditions might be so high as to endanger converter safety if continuously flowing. to prevent any damage during these conditions, it is customary to force the converter?s intermittent operation, in order to bring the average outp ut current to values such that the thermal stress for the transformer and the rectifiers can be easily handled. with the L6599AT the designer can externally program the maximum time t sh that the converter is allowed to run overloaded or under short-circuit conditions. overloads or short- circuits lasting less than t sh do not cause any other action , therefore providing the system with immunity to short duration phenomena. if, instead, t sh is exceeded, an overload protection (olp) procedure is activated that shuts down the L6599AT and, in the case of continuous overload/short-circuit, results in continuous intermittent operation with a user- defined duty cycle. ? ? ? ? ? ? ? ? ? ? ? a r crpkx b c c 1 i 8 . 0 r cr 2 c 2 a crpkx b x x r i 8 . 0 r a ? ? ?
application information L6599AT 22/32 docid15534 rev 7 figure 12. soft-start and delayed shutdown upon overcurrent timing diagram this function is realized with pin 2 (delay), by means of a capacitor c delay and a parallel resistor r delay connected to ground. as the voltage on the isen pin exceeds 0.8 v the first ocp comparator, in addition to discharging c ss , turns on an internal current generator that sources 150 a from the delay pin and charges c delay . during an overload/short-circuit, the ocp comparator and the internal current source is repeatedly activated and c delay is charged with an average current that depends esse ntially on the time constant of the current sense filtering circuit on c ss and the characteristics of the resonant circuit; the discharge due to r delay can be neglected, considering that the associated time constant is typically much longer. this operation continues until the voltage on c delay reaches 2 v, which defines the time t sh . there is no simple re lationship that links t sh to c delay , therefore it is more practical to determine c delay experimentally. as a rough indication, with c delay = 1 f, t sh is in the order of 100 ms. once c delay is charged at 2 v the internal switch that discharges c ss is forced low continuously regardless of the ocp comparator output, and the 150 a current source is continuously on, until the voltage on c delay reaches 3.5 v. this phase lasts: equation 9 with t mp expressed in ms and c delay in f. during this time the L6599AT runs at a frequency close to f start (see section 6.3: soft-start ) to minimize the energy inside the resonant circuit. as the voltage on c delay is 3.5 v, the L6599AT stops switching and the pfc_stop pin is pulled low. also the internal generator is turned off, so that c delay is now slowly discharged by r delay . the ic restarts when the voltage on c delay is less than 0.3 v, which takes: equation 10 $0y w 9ff &vv w w '(/$< 67$5783 29(5 /2$' 29(5/2$' w 3ulpdu\ &xuuhqw 1250$/ 23(5$7,21 1250$/ 23(5$7,21 6+87'2:1 9 9rxw w $ 62)767$57 62)767$ 57 9 9 9 0,132:(5 w 3) &b6723 ,6(1 w 9 7 6+ 7 6723 7 03 7 vv delay mp c 10 t ? ? delay delay 3 . 0 5 . 3 delay delay stop c r 5 . 2 ln c r t ? ?
docid15534 rev 7 23/32 L6599AT application information 32 the timing diagram of figure 12 shows this operation. note that, if, during t stop , the supply voltage of the L6599AT (v cc ) falls below the uvlo threshold, the ic records the event and does not restart immediately after v cc exceeds the startup thresh old if v(delay) is still higher than 0.3 v. also the pfc_stop pin stay s low as long as v(delay) is greater than 0.3 v. note also that, in the case of an overload lasting less than t sh , the value of t sh for the next overload is lower if they are close to one another. 6.5 latched shutdown the L6599AT is equipped with a comparator having the non-inverting input externally available at pin 8 (dis) and with the inverting i nput internally referenced to 1.85 v. as the voltage on the pin exceeds the internal threshold, the ic is immediately shut down and its consumption reduced to a low value. the informat ion is latched and it is necessary to let the voltage on the v cc pin go below the uvlo threshold to reset the latch and restart the ic. this function is useful to implement a latched overtemperature protection very easily by biasing the pin with a divider from an external reference voltage (e.g. pin 4, rf min ), where the upper resistor is an ntc ph ysically located close to a heating element like the mosfet, or the secondary diode or transformer. an ovp can be implemented as well, e.g. by sensing the output voltage and transferring an overvoltage condition via an optocoupler. 6.6 line sensing function this function basically stops the ic as the input voltage to the converter falls below the specified range and lets it restart as the voltage goes back within the range. the sensed voltage can be either the rectif ied and filtered mains voltage, in which case the function acts as a brownout protection, or, in systems wit h a pfc pre-regulator front-end, the output voltage of the pfc stage, in which case the function serves as a power-on and power-off sequencing. L6599AT shutdown upon input undervoltage is accomplished by means of an internal comparator, as shown in the block diagram of figure 13 , whose non-inverting input is available at pin 7 (line). the comparator is inte rnally referenced to 1.24 v and disables the ic if the voltage applied at the line pin is below the internal reference. under these conditions the soft-start is discharged, the pfc_stop pin is open and the consumption of the ic is reduced. pwm operation is re-ena bled as the voltage on the pin is above the reference. the comparator is provided with current hysteresis instead of a more usual voltage hysteresis: an internal 13 a current sink is on as long as the voltage applied at the line pin is below the reference and is o ff if the voltage is above the reference. this approach provides an additional degree of freedom: it is possible to set the on threshold and the off threshold separately by properly choosing the resistors of the external divider (see below). with voltage hysteresis, instead, fixing one threshold automatically fixes the other, depending on the built-in hysteresis of the comparator.
application information L6599AT 24/32 docid15534 rev 7 figure 13. line sensing function: inte rnal block diagram and timing diagram with reference to figure 11 , the following relationships can be established for the on (vin on ) and off (vin off ) thresholds of the input voltage: equation 11 which, solved for r h and r l , yields: equation 12 while the line undervoltage is active, the startup generator keeps on working but there is no pwm activity, therefore the v cc voltage (if not supplied by another source) continuously oscillates between the st artup and the uvlo thresholds, as shown in the timing diagram of figure 13 . as an additional safety measure (e.g. in case the low-side resistor is open or missing, or in non-power factor corrected systems in case of abnormally high input voltage), if the voltage on the pin exceeds 7 v, the L6599AT is shut do wn. if its supply voltage is always above the uvlo threshold, the ic restarts as the voltage falls below 7 v. the line pin, while the device is operating, is a high impedance input connected to high value resistors, therefore it is prone to pick-u p noise, which might alter the off threshold or give origin to undesired switch-off of the ic du ring esd tests. it is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nf) to prevent any malfunctioning of this $0y 9lq2. +9,qsxwexv 9 /,1( 9ff 9 ?$ 5 + 5 / +9,qsxwexv 9lq2. 9ff 9lq 21 9lq 2)) /9* +9* 9rxw /,1( 9 , +<6 ?$ w w w w w w w /$7 9lq2. +9,qsxwexv 9 /,1( 9ff 9 ?$ 5 + 5 / +9,qsxwexv 9lq2. 9ff 9lq 21 9lq 2)) /9* +9* 9rxw /,1( 9 , +<6 ?$ w w w w w w w l h off l 6 h on r 24 . 1 r 24 . 1 vin r 24 . 1 10 13 r 24 . 1 vin ? ? ? ? ? ? ? 24 . 1 vin 24 . 1 r r ; 10 13 vin vin r off h l 6 off on h ? ? ? ? ? ?
docid15534 rev 7 25/32 L6599AT application information 32 kind. if the function is not used, the pin must be connected to a voltage greater than 1.24 v but lower than 6 v (worst-case value of the 7 v threshold). 6.7 bootstrap section the supply of the floating high-side section is obtained by means of a bootstrap circuitry. this solution normally requires a high voltage fast recovery diode (d boot , figure 14 a) to charge the bootstrap capacitor c boot . in the L6599AT a patented integrated structure, replaces this external diode. it is realized by means of a high voltage dmos, working in the third quadrant and driven synchronously with the low-side driver (lvg), with a diode in series to the source, as shown in figure 14 b. figure 14. bootstrap supply: a) standard circuit; b) internal bootstrap synchronous diode the diode prevents any current being able to flow from the vboot pin back to v cc , in case the supply is quickly turned off when the internal capacitor of the pump is not fully discharged. to drive the synchronous dmos a voltage higher than the supply voltage v cc is necessary. this voltage is obtained by means of an internal charge pump ( figure 14 b). the bootstrap structure introduces a voltage drop while recharging cboot (i.e. when the low-side driver is on), which increases with the operating frequency and with the size of the external power mosfet. it is the sum of the drop across the r (ds)on and the forward drop across the series diode. at low frequency this drop is very small and can be neglected but, as the operating frequency increases, it must be taken into account. in fact, the drop reduces the amplitude of the driving sign al and can significantly increase the r (ds)on of the external high-side mosfet and then its conductive loss. $0y d e 287 9%227 9f f ' %227 & %227 '$3 287 9%227 9ff /9* & % 227 /$ d e 287 9%227 9f f ' %227 & %227 '$3 287 9%227 9ff /9* & % 227 /$7
application information L6599AT 26/32 docid15534 rev 7 this concern applies to converters designed with a high resonance frequency (indicatively, > 150 khz), so that they run at high frequency also at full load. otherwise, the converter runs at high frequency at light load, where the current flowing in the mosfets of the half bridge leg is low, so that, generally, an r (ds)on rise is not an issue. howeve r, it is wise to check this point anyway and the following equation is usef ul to compute the drop on the bootstrap driver: equation 13 where q g is the gate charge of t he external power mosfet, r (ds)on is the on-resistance of the bootstrap dmos (150 w, typ.) and t charge is the on-time of the bootstrap driver, which equals about half the switching period minus the deadtime t d . for example, using a mosfet with a total gate charge of 30 nc, t he drop on the bootstrap driver is about 3 v at a switching frequency of 200 khz: equation 14 if a significant drop on the bootstrap driver is an issue, an external ultra-fast diode can be used, therefore saving the drop on the r (ds)on of the internal dmos. f on ) ds ( e arg ch g f on ) ds ( e arg ch drop v r t q v r i v ? ? ? ? v 7 . 2 6 . 0 150 10 27 . 0 10 5 . 2 10 30 v 6 6 9 drop ? ? ? ? ? ? ? ? ? ?
docid15534 rev 7 27/32 L6599AT application information 32 figure 15. application example: 90 w ac/dc adapter using l6563h, L6599AT and srk2000 $0y
package information L6599AT 28/32 docid15534 rev 7 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at www.st.com . ecopack is an st trademark.
docid15534 rev 7 29/32 L6599AT package information 32 7.1 so16n package information figure 16. so16n package outline table 6. so16n package mechanical data symbol dimensions (mm) min. typ. max. a 1.75 a1 0.10 0.25 a2 1.25 b0.31 0.51 c0.17 0.25 d 9.80 9.90 10.00 e 5.80 6.00 6.20 e1 3.80 3.90 4.00 e1.27 h0.25 0.50 l0.40 1.27 k0 8 ccc 0.10 b )
package information L6599AT 30/32 docid15534 rev 7 figure 17. so16n recommended footprint (dimensions are in mm)
docid15534 rev 7 31/32 L6599AT revision history 32 8 revision history table 7. document revision history date revision changes 05-jun-2009 1 initial release. 11-aug-2009 2 updated table 5 on page 9 . 30-oct-2009 3 updated table 5 on page 9 . 08-mar-2013 4 updated table 1: device summary updated section 7: package information and table 3: absolute maximum rating . general text and grammatical corr ections throughout the document. 11-aug-2014 5 updated section 5: electrical characteristics on page 9 (updated t j , removed ?max.? value from v z symbol in table 5 ). updated section 7: package information on page 28 (updated titles, reversed order of figure 16 and figure 6 , minor modifications). minor modifications throughout document. 18-aug-2014 6 updated table 3 on page 8 (replaced -40 by -50 c for tj symbol). 29-jul-2015 7 updated the junction temperature operating range (t j ) in table 3 and section 5 . added section title so16n package information (added title only. no change to so16n package information content)
L6599AT 32/32 docid15534 rev 7 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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